1. Field of the Invention
This invention relates to a method of erasing data on a non-volatile semi-conductor memory, and more particularly to a method of erasing data on a non-volatile semi-conductor memory wherein a large number of field effect transistors each having a floating gate electrode are arrayed as memory cells.
2. Description of Related Art
FIG. 1(A) is a circuit diagram of a memory cell of a non-volatile semi-conductor memory wherein a large number of field effect transistors (hereinafter referred to as FETs) each having a floating gate electrode are arrayed as memory cells, and FIG. 1(B) is a sectional view showing the structure of the memory cell.
The memory cell shown in FIGS. 1(A) and 1(B) includes P-type silicon substrate 1, tunnel oxide film 2 formed by using a silicon thermal oxidation technique, a thin film forming technique based on the CVD (chemical vapour deposition) method, a photolithography technique, a thin film dry etching technique or some other suitable technique, floating gate electrode FG of polycrystalline silicon, interlayer insulator film 3, a gate electrode portion of the two polycrystalline silicon layer type, and source electrode S and drain electrode D of a diffused layer formed by using an ion implantation technique of phosphor or arsenic. In the non-volatile memory, electrons are accumulated into floating gate electrode FG through tunnel oxide film 2 to raise the threshold level voltage of the FET memory cell at control gate electrode CG in order to write data, and the electrons are removed from floating gate electrode FG through tunnel oxide film 2 to lower the threshold level voltage in order to erase the data.
In the non-volatile memory described above, it is known that the threshold levels of the memory cells after erasure of data disperse within a range of several volts due to dispersion in film thickness, film quality or working accuracy of tunnel oxide film 2 of the memory cells. As one countermeasure for suppressing dispersion, a method which makes use of injection of hot carriers into the floating gate electrodes arising from the drain avalanche phenomenon is conventionally known (Seiji Yamada, Technical Digest of 1991 International Electron Devices Meeting, pp.307-310).
An outline of the method is described with reference to FIG. 5. FIG. 5 is a diagram showing the relationship of gate current I.sub.g to floating gate voltage V.sub.fg*, and control gate voltage V.sub.cg when floating gate electrode FG is charged positively.
When the relationship between source-drain voltage V.sub.ds and floating gate voltage V.sub.fg is V.sub.ds &gt;V.sub.fg, hot carriers generated by the source-drain current are injected into floating gate electrode FG. The types of hot carriers depend upon the floating gate voltage, and are classfied, from the low voltage side as, hot holes (in the area of (H.H.) in FIG. 5) originating in a drain avalanche phenomenon, hot electrons (in the area of (H.E.) in FIG. 5) originating from a drain avalanche phenomenon, and channel hot electrons (in the area of (C.H.E.) in FIG. 5). It is important here that, when the floating gate voltage increases to the level indicated by V.sub.fg * in FIG. 5, hot carriers are not injected into floating gate electrode FG any more and the polarity of the carrier charge is reversed. As a result, when, for example, the floating gate voltage is higher than V.sub.fg * and the relationship of V.sub.ds &gt;V.sub.fg is satisfied, a feedback mechanism in which injection of hot electrons into floating gate electrode FG drops the floating gate voltage and the drop of the floating gate voltage reduces the injection amount of hot electrons is formed between the floating gate voltage and the hot electron injection amount, so that the floating gate voltage converges to V.sub.fg *.
Timings of voltage application to the electrodes in order to actually erase data are described with reference to FIG. 6.
First, drain electrode D is set to 0 volt and -13 V is applied to control gate electrode CG while a pulse of 5 V is applied for 0.1 second to source electrode S to remove electrons accumulated in floating gate electrode FG by an F-N (Fowler-Nordhein) tunnel current, and then so-called excessive erasure is performed to accumulate positive holes to charge floating gate electrode to V.sub.fg * =2.0 V or more.
Then, control gate electrode CG is set to 0 V, and a pulse of 5.0 V is applied for 0.5 seconds to source electrode S. As a result of the disposition, the feedback mechanism between the floating gate electrode and the hot electron injection amount described above operates so that the floating gate voltage converges to 2.0 V. As a result, the threshold level of control gate electrode CG after data erasure also converges to a fixed value, which can suppress possible fluctuation of the threshold levels of the memory cells. In fact, the threshold level voltage can be controlled within a range of about 0.7 V depending upon the dispersion of the configuration of source electrode S or some other factor.
With the conventional method of erasing data on a non-volatile semi-conductor memory described above, however, since the drain avalanche phenomenon is used for erasure, there is a problem in that source electrode S and drain electrode D suffer from some damage, resulting in degradation of the voltage-withstanding property of the junction between the diffused layer of the electrodes and the substrate.
Further, in order to make the threshold voltages of the memory cells uniform after an erasure, positive holes are injected into floating gate electrode FG so as to effect excessive erasure upon each erasure. Accordingly, since the injection of positive holes accelerates degradation of tunnel oxide film 2, there is another problem that the switching characteristic between writing and erasure is degraded by the degradation of tunnel oxide film 2.
Furthermore, in order to make the threshold voltages uniform after erasure of data, the source-drain current for causing the drain avalanche phenomenon is required, in addition to electrons to flow into floating gate electrode FG. Accordingly, there is a further problem in that the disposition to make the threshold voltages uniform after erasure of data results in higher power dissipation.